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1. Field of the Invention
The present invention relates to development of integrated circuits; and more particularly to the tools used in design and development of application specific integrated circuits.
2. Description of Related Art
Automated design tools for application specific integrated circuit (ASIC) designs enable ASIC designs involving millions of usable gates in a single chip. The process of development of such complex ASICs relies on the development and verification tools executed in data processing systems which automate the design. These tools are provided by major electronic design automation or ASIC vendors, such as LSI Logic Corporation, the assignee of the present application. For instance, LSI Logic provides a product known as the C-MDE (trademark) design tools, which provide all the functions necessary to take a design to working silicon. The design tools in commercially available design automation systems include timing analysis tools, floor planning tools, layout tools, synthesis tools, packaging tools and more.
The design process typically involves specification of an ASIC with a behavioral (or register transfer level) description. In a process known as synthesis, the behavioral description is then processed to create an optimized gate-level netlist for the design. With millions of gates in a single design, the netlist becomes very large. Because synthesis is a recursive process, the entire netlist must be stored in the data processing system and processed before it is created in its final form.
As ASIC designs become increasingly more dense, the available computing capability is having difficulty in keeping pace. Thus, systems executing tools for ASIC design require powerful computers with large amounts of memory. As the number of usable gates explodes, speed and memory bottlenecks are created which substantially slow down the development process of complex designs.
In order to address this problem, one electronic design automation vendor, known as Synopsys, provides for a xe2x80x9cmodelxe2x80x9d using which a hierarchical design can be converted into library cells with delay information for the cells in the form of timing arcs. This model is substituted for the original design and the original design can be removed from memory during the bottom up synthesis process for the design. This technique proves to be inaccurate, not only on its own environment, but also when the model is transported to a new environment. The synthesis relying on such model results in designs very different from that obtained using the actual gate level netlists of the modeled block. An unacceptable amount of accuracy is lost according to this technique while trying to reduce memory requirements.
Also, as the ASIC industry matures, many vendors provide proprietary core blocks of circuits to users of the ASIC design tools. These proprietary circuits substantially reduce the design time required for ASIC development. However, the vendor of such circuits must disclose details of the design of the core circuit for use in synthesis of the entire ASIC. This results in undesirable disclosure of proprietary information which might otherwise be held confidential.
Accordingly, it is desirable to provide a tool which aids in improving compilation speed and reduces memory requirements during hierarchical synthesis of large ASIC designs without sacrificing accuracy. Further, it is desirable that the result of execution of such a tool is portable across design environments and synthesis tools to facilitate design re-use. Furthermore, it is desirable to provide information about a proprietary module in a format which protects the intellectual property of the owner of the module, while allowing accurate synthesis of ASICs using the module.
The present invention provides a practical approach for synthesis of million gate ASICs based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized block. This gate level description is reduced by removing internal gates to produce a gate level synthesis shell which is a subset of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, output drive of the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists. Thus, the synthesis shell can be used for hierarchical synthesis in a customer""s design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider. Since all the information that is needed by a synthesizer is available in the synthesis shell in netlist form, and additional information is provided to reconstruct original loading and area information, the shell is extremely accurate.
The synthesis shell as mentioned above comprises a gate level description which is a subset of the synthesized block. This reduced description is obtained by deleting elements of the gate level description according to a set of criteria including the following:
preserve combinatorial paths from an input port to a first storage element;
preserve combinatorial paths from a last storage element to an output port;
preserve direct combinatorial paths from an input port to an output port;
preserve clock distribution paths;
preserve feedback paths from an output port to a storage element, along with the storage element;
preserve feedback paths to direct combinatorial paths in the design;
preserve asynchronous RAM if a write signal to the asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic, and treat synchronous RAMs like storage elements;
preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, either through combinatorial logic or directly; and
preserve asynchronous paths like reset, clear, et cetera.
Generation of the synthesis shell also includes the step of generating area difference data indicating differences between the area needed for the original block, and the area needed for preserved elements in the synthesis shell, and including the area difference data with the synthesis shell. Further, load information is stored with the synthesis shell indicating the loads within the synthesis shell relevant to the synthesis process, including the loads on each node in a path from a last storage element to an output in the block, and incremental loads on clock and asynchronous paths, where an incremental load is a load on a net compensating for removal of gates connected to the net.
The straightforward implementation of a shell is represented in the form of a netlist, albeit a subset of the original netlist for the block subject of the shell. The shell maintains enough information in the subset of the netlist such that if the original netlist was replaced by this subset it would make no difference to the synthesizer and it would still continue to have access to all the information that it could have obtained from the original netlist. The size of the shell netlist is much smaller, as it is by construction a subset of the original netlist. Thus memory requirements to store the shell netlist are lesser. The shell, which is portable across different process, voltage, and temperature (PVT) conditions, can be made for delivery by a vendor to designers of integrated circuits, or it can be generated by a designer during hierarchical synthesis.
Thus, the present invention can be characterized as a method for synthesizing a gate level description of an integrated circuit module which includes a plurality of blocks from a behavioral or register transfer level description of the module. The method includes propagating design constraints to synthesize the first block in the plurality from the behavioral description of the block. This synthesized, gate level description is reduced to a synthesis shell as discussed above. Next, the method involves synthesizing a second block in the plurality of blocks by processing the behavioral description of the second block with reference to the synthesis shell to produce a gate level description of the at least one other block.
The method of synthesizing the integrated circuit module may further include synthesizing yet another block in the plurality by processing the behavioral description of the other block with reference to the synthesis shells of the first and second blocks in a recursive fashion until the entire design is completed.
Furthermore, the process may include the steps of merging synthesis shells of two blocks into a higher level synthesis shell. The merged file is then reduced into a merged synthesis shell which can replace the combination of lower level synthesis shells.
The present invention can also be characterized as a machine which includes resources to execute the method described above to create synthesis shells and/or stores a synthesis shell made according to the methods described above, and which also includes processing resources for executing synthesis algorithms which utilize synthesis shells.
Accordingly, a practical technique is provided to reduce the amount of processing time, and memory required for synthesizing large ASICs having millions of gates. According to the prior art, synthesis of large designs has caused the compute capacity available to burst at the seams, creating speed and resource bottlenecks. The primary reasons for these bottlenecks is the fact that the entire design netlist has to be kept in memory according to the prior art while synthesis takes place, even blocks in which optimization has been completed. The presence of a synthesized block in memory is required because it may have an impact on the characterization of other blocks under synthesis. The synthesis shell according to the present invention is based on an extraction of the relevant information from a synthesized block such that the characterization of another block under synthesis is still accurate. The advantage gained from this shell is a dramatic decrease in the memory requirement to store the extracted block as opposed to storing the entire netlist of the synthesized block in memory. Accordingly, the advantages of the present invention include the following:
1. reduction in memory requirements;
2. reduction in run time;
3. exact substitute for original design in terms of accuracy of representation and accuracy of use in hierarchical design synthesis;
4. relies on a netlist approach to the synthesis shell which is portable across the synthesis tools and design environments;
5. preserves accuracy of information for use in systems that provide previously designed cells to designers for use in their own ASICs;
6. fits hierarchical top down characterization and bottom up optimization methodologies used in synthesis of an ASICs;
7. protects the intellectual property for proprietary cores represented by the shells.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description, and the claims which follow.